GS2962 Datasheet, PDF (33/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
3FF
3FF
000
000
000
0 0 0 X Y Z (EAV) X Y Z (EAV)
H V F T IM IN G A T E A V
3FF
3FF
000
000
000
000
X Y Z (SAV) X Y Z (SAV)
H V F T IM IN G A T S A V
Figure 4-6: H:V:F Input Timing - HD 10-bit Input Mode
PCLK
C H R O M A D A T A IN P U T
LU M A D ATA IN P U T
H
V
F
3FF
000
000
X Y Z (EAV)
H S IG N A L T IM IN G :
H _C O N F IG = LO W
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
Figure 4-7: H:V:F Input Timing - SD 20-bit Mode
PC LK
M U L T IP LE X E D Y 'C b C r D A T A IN P U T
H
V
F
3FF
000
H S IG N A L T IM IN G :
000
X Y Z (EAV)
H _C O N F IG = LO W
Figure 4-8: H:V:F Input Timing - SD 10-bit Mode
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
4.3.2 CEA 861 Timing
The GS2962 extracts timing information from externally provided HSYNC, VSYNC, and
DE signals when CEA 861 timing mode is selected by setting DETECT_TRS = LOW and
TIM_861 = HIGH.
Horizontal sync (H), Vertical sync (V), and Data Enable (DE) timing must be provided via
the H/HSYNC, V/VSYNC and F/DE input pins. The host interface register bit H_CONFIG
is ignored in CEA 861 input timing mode.
The GS2962 determines the EIA/CEA-861 standard and embeds EAV and SAV TRS
words in the output serial video stream.
Video standard detection is not dependent on the HSYNC pulse width or the VSYNC
pulse width and therefore the GS2962 tolerates non-standard pulse widths. In addition,
the device can compensate for up to ±1 PCLK cycle of jitter on VSYNC with respect to
HSYNC and sample VSYNC correctly.
NOTE 1: The period between the leading edge of the HSYNC pulse and the leading edge
of Data Enable (DE) must follow the timing requirements described in the EIA/CEA-861
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
33 of 82