GS2962 Datasheet, PDF (27/82 Pages) Gennum Corporation – Integrated Narrow-Bandwidth PLL

4.2 Parallel Data Inputs
Data signal inputs enter the device on the rising edge of PCLK, as shown in Figure 4-1.
DDR interface
NOTE: DS = Data Stream as per SMPTE 425M
3.36ns
PCLK
TH
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
DS1_n-1
transition zone
DS2_* is launched on the
negative edge of PCLK
by the source chip to the
GS2962
DS1_* is launched on the
positive edge of PCLK
by the source chip to the
GS2962
TSU
TH
DS1_n-1
DS2_0
transition zone
TSU
TH
DS2_0
DS1_0
transition zone
DS1_0
SDR interface
DS* is launched on the positive edge of PCLK
by the source chip to the GS2962
PCLK period
PCLK
TH
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
data_0
transition zone
TSU
TH
data_0
Figure 4-1: GS2962 Video Host Interface Timing Diagrams
data_1
transition zone
TSU
TH
data_1
Table 4-1: GS2962 Digital Input AC Electrical Characteristics
Parameter
Input data set-up time
Input data hold time
Input data set-up time
Input data hold time
Symbol
t_SU
t_IH
t_SU
t_IH
Conditions
50% levels;
1.8V operation
50% levels;
3.3V operation
Min
Typ
Max
1.2
−
−
0.8
−
−
1.3
−
−
0.8
−
−
Units
ns
ns
ns
ns
Table 4-2: GS2962 Input Video Data Format Selections
Input Data Format
Pin/Register Bit Settings
20-bit demultiplexed 3G
format
20-bit data Input
3G format
20BIT
/10BIT
HIGH
HIGH
RATE
_SEL0
LOW
LOW
RATE
_SEL1
HIGH
SMPTE
_BYPASS
HIGH
DVB_ASI
LOW
HIGH
LOW
LOW
DIN[9:0]
Data Stream
Two
DATA
DIN[19:10]
Data Stream One
DATA
GS2962 3G/HD/SD-SDI Serializer with Complete
SMPTE Video Support
Data Sheet
48005 - 7
October 2010
27 of 82