MB85RS16NPNF-G Datasheet, PDF (9/36 Pages) Fujitsu Component Limited. – 16 K (2 K × 8) Bit SPI

MB85RS16N
• READ
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ
are input to SI. The 5-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keeps on reading with automatic address increment which is enabled by con-
tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant
address, it rolls over to the starting address, and reading cycle keeps on infinitely.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
OP-CODE
16-bit address
0 0 0 0 0 0 1 1 X X X X X 10
MSB
High-Z
543210
LSB _MSB
76
Invalid
Data Out LSB
543210
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The 5-bit upper address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command. However,
if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing
with automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle keeps on infinitely.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
OP-CODE
16-bit address
Data In
0 0 0 0 0 0 1 0 X X X X X 10
543210 76543210
MSB
LSB MSB
LSB
High-Z
DS501-00030-3v0-E
9