MB85RS16NPNF-G Datasheet, PDF (11/36 Pages) Fujitsu Component Limited. – 16 K (2 K × 8) Bit SPI

MB85RS16N
■ BLOCK PROTECT
Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
600H to 7FFH (upper 1/4)
1
0
400H to 7FFH (upper 1/2)
1
1
000H to 7FFH (all)
■ WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
WEL
WPEN
WP
Protected Blocks Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The
timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a
HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin
transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the
same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H”
level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs
become don’t care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during
hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the
value before transition to hold status.
CS
SCK
HOLD
Hold Condition
Hold Condition
DS501-00030-3v0-E
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