MB85RS16NPNF-G Datasheet, PDF (6/36 Pages) Fujitsu Component Limited. – 16 K (2 K × 8) Bit SPI

MB85RS16N
■ STATUS REGISTER
Bit No.
Bit Name
7
WPEN
6 to 4
⎯
3
BP1
2
BP0
1
WEL
0
0
Function
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN protects
writing to a status register (see “■ WRITING PROTECT”) relating with WP
input. Writing with the WRSR command and reading with the RDSR com-
mand are possible.
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible. These bits are not used but they are read with the
RDSR command.
Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (see “■ BLOCK PROTECT”). Writ-
ing with the WRSR command and reading with the RDSR command are
possible.
Write Enable Latch
This indicates FRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
After power ON.
After WRDI command recognition.
At the rising edge of CS after WRSR command recognition.
At the rising edge of CS after WRITE command recognition.
This is a bit fixed to “0”.
■ OP-CODE
MB85RS16N accepts 7 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting
op-code, the command are not performed.
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
RDID
Read Device ID
1001 1111B
6
DS501-00030-3v0-E