MB15F03 Datasheet, PDF (9/22 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F03
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
NNNNNNNNNNN
11 10 9 8 7 6 5 4 3 2 1
5
00000000101
6
00000000110
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
11111111111
Note: • Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
AAAAAAA
7654321
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = ”H”
Prescaler
divide ratio
IF-PLL
RF-PLL
16/17
64/65
SW = ”L”
32/33
128/129
9