MB15F03 Datasheet, PDF (8/22 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F03
Programmable Counter
LS
Data
MS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CC L S F A A A A A A A N N N N N NN NN NN
N N D W C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11
12 S
CNT1, 2 : Control bit
N1 to N14 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW
: Divide ratio setting bit for the prescaler
(16/17 or 32/33 for the IF-PLL, 64/65 OR 128/129 for the RF-PLL)
FC
: Phase control bit for the phase detector
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
RRRRRRRRRRRRRR
14 13 12 11 10 9 8 7 6 5 4 3 2 1
5
00000000000101
6
00000000000110
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
11111111111111
Note: • Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
T
T
1
2
LD/fout pin state
L
L
Outputs frIF.
H
L
Outputs frRF.
L
H
Outputs fpIF.
H
H
Outputs fpRF.
8