MB15F03 Datasheet, PDF (3/22 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F03
s PIN DESCRIPTIONS
Pin No.
SSOP BBC
1
16
Pin
name
GNDRF
2
1
OSCin
3
2
GNDIF
4
3
finIF
5
4
VccIF
6
5
LD/fout
7
6
PSIF
8
7
DoIF
9
8
DoRF
10
9
PSRF
11
10
XfinRF
12
11
VccRF
13
12
finRF
14
13
LE
15
14
Data
16
15
Clock
I/O
Descriptions
– Ground for RF–PLL section.
I
The programmable reference divider input. TCXO should be connected
with a coupling capacitor.
– Ground for the IF-PLL section.
I
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
–
Power supply voltage input pin for the IF-PLL section.
When power is OFF, latched data of IF-PLL is cancelled.
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
O The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
LDS bit = ”L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
I
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode
PSIF = ”L” ; Power saving mode
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Power saving mode control for the RF-PLL section. This pin must be set
I
at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode
PSRF = ”L” ; Power saving mode
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the RF-PLL section, the shift register
– and the oscillator input buffer. When power is OFF, latched data of RF-
PLL is cancelled.
I
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
I
When LE is ”H”, data in the shift register is transferred to the
corresponding
latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
I
A data is transferred to the corresponding latch (IF-ref counter, IF-Prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
I One bit data is shifted into the shift register on a riging edge of the
clock.
3