DS07-16303-3E Datasheet, PDF (65/97 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91121
(2) Clock Timing Rating
Parameter
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 .0V, TA = 0 °C to + 70 °C)
Value
Symbol Pin name Condition
Unit
Min. Max.
Remarks
Clock frequency (1)
Clock cycle time
Frequency shift ratio*¹
(when locked)
Clock frequency (2)
FC
X0, X1
tC
X0, X1

∆f
FC
X0, X1
10
12.5 MHz
80
100
ns _{When using PLL}

5
%
10
25
MHz
Self-oscillation
(divide-by-2 input)
Clock frequency (3)
Clock cycle time
FC
X0, X1
tC
X0, X1
Input clock pulse width
PWH, PWL X0, X1
Input clock rising/falling time
Internal operating clock
frequency
Internal operating clock
cycle time
tCR, tCF
fCP
fCPB
fCPP
tCP
tCPB
tCPP
X0, X1
10
25
MHz
External clock
(divide-by-2 input)

40
100
ns
25

ns Input to X0 only
10

ns Input to X0, X1

8
ns (tCR + tCF)
0.625*²
50
MHz CPU system
0.625*² 25*³ MHz Bus system
0.625*²
25
MHz Peripheral system

20 1600*² ns CPU system
40*³ 1600*² ns Bus system
40 1600*² ns Peripheral system
*1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock
multiplication system.
∆f = ^{| α |} × 100 (%)
f0
+
+α
Center frequency f0
−α
−
*2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and
a 1/8 gear.
*3 : Values when using the doublure and CPU operation at 50 MHz.
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