DS07-16303-3E Datasheet, PDF (2/97 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91121
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• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead time in branch executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (push PC and PS) : 6 cycles, 16 priority levels
2. Bus interface
• Clock doubler : Internal 50 MHz, external bus 25 MHz operation
• 25-bit address bus (32 Mbytes memory space)
• 8/16-bit data bus
• Basic external bus cycle : 2 clock cycles
• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6
• Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured as input/output ports.
• Little endian mode supported (Select 1 area from area 1 to 5)
3. DRAM interface
• 2 banks independent control (area 4 and 5)
• Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM
• Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode
• Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles
• DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
4. DSP Macros (Simplified DSP)
• High-speed multiply-accumulate operation (1 machine cycle)
• Data format :
16-bit fixed-point (16 × 16 + 40 bits)
• Instruction area :
256 words × 16 bits
• Data area :
64 words × 16 bits × 1 set, 1024 words × 16 bits × 2 sets (banks)
• Capable of rounding and saturation processing
• Number of terms in addition : Up to 32 terms
• Instructions :
MAC, STR, and JMP instructions
• Delay processing :
Capable of free transfer within 32 words
• Fixed-point system :
Capable of selection from among Q12 to Q15
• Program execution control : Capable of externally selecting eight calculation programs
• Variable monitoring :
Capable of monitoring calculation results of up to 4 words without stopping the
program
• Efficient data variable areas : Two banks of data variable areas provided, enabling the CPU to execute a DSP
calculation program using one bank while accessing a data variable in the other.
5. Cache memory
• 1 K-byte instruction cache
• 2-way set-associative configuration
• 32 blocks/way, 4 entries (4 words) /block
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