DS07-16303-3E Datasheet, PDF (51/97 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91121
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
• Block diagram
INT0 ²
IM
NMI
RI00
•
•
•
RI47
(DLYIRQ)
OR
•
•
•
DLYI ¹
Priority judgment
5
NMI processing
4
Level judgment
ICR00
6
• _{Vector judgment}
•
ICR47
Level
vector
generation
5
HLDREQ
cancel
request
6
LEVEL4 to
LEVEL0 ⁴
HLDCAN ³
VCT5 to
VCT0 ⁵
R-bus
*1 : DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section
“11. Delayed Interrupt Module” for detail) .
*2 : INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3 : HLDCAN is a bus release request signal for bus masters other than CPU.
*4 : LEVEL5 to LEVEL0 are interrupt level outputs.
*5 : VCT5 to VCT0 are interrupt vector outputs.
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