MB86961A Datasheet, PDF (6/29 Pages) Fujitsu Component Limited. – UNIVERSAL INTERFACE FOR 10BASET

MB86961A
APPLICATIONS
Figure 1 shows the MB86961A in a typical application,
interfacing between a controller and the RJ45 connector
of the twisted-pair network. Figures 2 through 5 show
detailed diagrams of various MB86961A applications.
AUTO PORT SELECT LOOPBACK
CONTROL PIN
With MD0 and MD1 both tied high, the MB86961A logic
and framing are set to Mode 4 (compatible with National
NS8390 controllers).
The AUTOSEL pin is tied high, allowing the MB86961A
to automatically select the active port. The high at LI
enables Link Testing.
The UTP and NTH pins are both tied high selecting the
standard receiver threshold and 100 Ω termination for
unshielded TP cable. (See Figure 2.)
MANUAL PORT SELECT LINK
TEST FUNCTION
With MD0 low and MD1 tied high, the MB86961A logic
and framing are set to Mode 3 (compatible with Fujitsu’s
MB86960 controller). As in Figure 3, the LI pin is tied
high, enabling Link Testing, and the UTP and NTH pins
are both tied high, selecting the standard receiver thresh-
old and 100 Ω termination for unshielded TP cable. How-
ever, in this application AUTOSEL is tied low, allowing
external port selection through the PAUI pin. The remote
status output are inverted and used to drive LED indica-
tors. (See Figure 3.)
TWISTED-PAIR ONLY
Figure 4 shows the MB86961A is a typical twisted-pair
only application. The DTE is connected to a 10BASE-T
network through the twisted-pair RJ45 connector. (The
AUI port is not used.) With MD0 tied high and MD1
grounded, the MB86961A logic and framing are set to
Mode 2 (compatible with Intel 82586 controllers). The LI
pin externally controls the link test function. The UTP
and NTH pins are both tied low, selecting the reduced
receiver threshold and 150 Ω termination for shielded TP
cable. The switch at LEDT/PDN manually controls the
power down mode. (See Figure 4.)
AUI ENCODER/DECODER ONLY
In this application, the DTE is connected to the coaxial
network through the AUI. AUTOSEL and PAUI are both
tied to ground, manually selecting the AUI port. The
twisted-pair port is not used. With MD1 and MD0 both
grounded, the MB86961A logic and framing are set to
Mode 1 (compatible with AMD AM7990 controllers).
The LI pin is tied low, disabling the link test function.
The LBK input controls loopback. A 20 MHz crystal con-
nected across CLKI and CLK0 provides the required
clock signal. (See Figure 5.)
10BASE-T
AUI
MB86961A
10BASE-T Inter-
MB86960
Ethernet
H
O
S
B
U
Figure 1. Typical System Diagram
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