MB86961A Datasheet, PDF (14/29 Pages) Fujitsu Component Limited. – UNIVERSAL INTERFACE FOR 10BASET

MB86961A
When the AUI port is selected and LBK=1, data transmit-
ted by the back-end controller is internally looped back
from the TXD pin through the Manchester encoder/decod-
er to the RXD pin. When LBK=0, no AUI loopback occurs.
LINK INTEGRITY TEST
Figure 10 is a state diagram of the MB86961A Link
Integrity test function. The link integrity test is used to
determine the status of the receive side twisted-pair cable.
Link integrity testing is enabled when pin 8 (LI) is tied
high. When enabled, the receiver recognizes link integrity
pulses which are transmitted in the absence of receive
traffic. If no serial data stream or link integrity pulses are
detected within 50-150 ms, the chip enters a link fail state
and disables the transmit and normal loopback functions.
The MB86961A ignores any link integrity pulse with an
interval less than 2-7 ms. The MB86961A will remain in
the link fail state until it detects either a serial data packet
or two or more link integrity pulses.
Power On
IDLE TEST
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
(Link_Loss_Timer_Done) •
(TPI = Idle)
(Link_Test_Rcvd = False)
(TPI = Active)
((Link_Test_Rcvd = True) •
(Link_Test_Min_Timer_Done))
LINK TEST FAIL RESET
Link_Count = 0
XMIT = Disable
RCVR = Disable
LPBK= Disable
(TPI = Active)
(Link_Test_Rcvd = False) •
(TPI = Idle)
LINK TEST FAIL WAIT
XMIT = Disable
RCVR = Disable
LPBK= Disable
Link_Count = LInk Count + 1
(Link_Test_Rcvd = Idle) •
(TPI = Idle)
(TPi = Active) +
(Link_Count = LC_Max)
LINK TEST FAIL EXTENDED
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT = Disable
(TPI = Idle) •
(DO = Idle)
LINK TEST FAIL
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT = Disable
RCVR = Disable
LPBK = Disable
(Link_Test_Min_Timer_Done)•
(Link_Test_Rcvd = True)
(TPI = Idle • Link_Test_Max_Timer_Done) +
((Link_Test_Min_Timer_Done) •
(Link_Test_Rcvd = True))
Figure 10. Link Integrity Test Function
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