 English |
|
|
|
|
|
|
|
| MB86961A Datasheet, PDF (25/29 Pages) Fujitsu Component Limited. – UNIVERSAL INTERFACE FOR 10BASET | |||
| |||
| ◁ |
MB86961A
MODE 4 (MD1=1, MD0=1) TIMING DIAGRAMS â FIGURES 30 - 35
TPIP/TPIN
CD
10101010111010001010
tCD
RCLK
RXD
tDATA
tRDH
tRDS
1 0 1 0 1 0 1 0 1 1 1 01
Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 30. Mode 4 RCLK/SOP Timing
TPIP/TPIN
101010100
CD
tRD
RCLK
tCDOFF
tIFG
RXD
101010100
Note: RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 31. Mode 4 RCLK/EOP Timing
25
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese