MB86961A Datasheet, PDF (11/29 Pages) Fujitsu Component Limited. – UNIVERSAL INTERFACE FOR 10BASET

MB86961A
FUNCTIONAL DESCRIPTION
The MB86961A Universal Ethernet Interface Transceiver
performs the physical layer signaling (PLS) and Media
Attachment Unit (MAU) functions as defined by the
IEEE 802.3 specification. It functions as a PLS-only
device (for use with 10BASE2 or 10BASE5 coaxial cable
networks) or as an Integrated PLS/MAU (for use with
10BASE-T twisted-pair networks).
The MB86961A interfaces a back-end controller to either
an AUI drop cable or twisted-pair (TP) cable. The con-
troller interface includes transmit and receive clock and
NRZ data channels, as well as mode control logic and
signaling. The AUI interface comprises three circuits:
Data output (DO), Data Input (DI) and Collision (CI).
The twisted-pair interface comprises two circuits:
Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO).
In addition to the three basic interfaces, the MB86961A
contains an internal crystal oscillator and four LED driv-
ers for visual status reporting.
Functions are defined from the back end controller side of
the interface. The MB86961A Transmit function refers to
data transmitted by the back end to the AUI cable (PLS-
Only mode) or to the twisted-pair network (Integrated
PLS/MAU mode). The MB86961A Receive function
refers to data received by the back end from the AUI
cable (PLS-Only) or from the twisted-pair network (Inte-
grated PLS/MAU mode). In the integrated PLS/MAU
mode, the MB86961A performs all required MAU func-
tions defined by the IEEE 802.3 10BASE-T specification
such as collision detection, link integrity testing, signal
quality error messaging, jabber control and loopback. In
the PLS-Only mode, the MB86961A receives incoming
signals from the AUI DI circuit with up to 18ns of jitter
and drives the AUI DO circuit.
CONTROLLER COMPATIBILITY MODES
The MB86961A is compatible with most industry stan-
dard controllers including devices produced by Advanced
Micro Devices (AMD), Intel, Fujitsu and National Semi-
conductor. Four different control signal timing and polar-
ity schemes (Modes 1 through 4) are required to achieve
this compatibility. Mode select pins MD0 and MD1
determine controller compatibility modes as listed in
Table 1.
Table 1. MB86961A Compatibility Modes
MD1 MD0
0
0 Mode 1:
0
1 Mode 2:
1
0 Mode 3:
1
1 Mode 4:
Mode
Compatible with Advanced
Micro Devices AM7990 con-
trollers
Compatible with Intel 82586
controllers
Compatible with Fujitsu’s
MB86960 controller
Compatible with National
Semiconductor 8390 control-
lers
• Mode 1: Figures 12-17
• Mode 2: Figures 18-23
• Mode 3: Figures 24-29
• Mode 4: Figures 30-35
The related timing specifications are provided in the elec-
trical characteristics section of this data sheet.
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