MB86961A Datasheet, PDF (21/29 Pages) Fujitsu Component Limited. – UNIVERSAL INTERFACE FOR 10BASET

MB86961A
MODE 2 (MD1=0, MD0=1) TIMING DIAGRAMS — FIGURES 18 - 23
TPIP/TPIN
CD
10101010111010001010
t_CD
RCLK
RXD
t_DATA
t_RDH
t_RDS
1 0 1 0 1 0 1 0 1 1 1 01
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 18. Mode 2 RCLK/SOP Timing
TPIP/TPIN
101010100
CD
t_RD
RCLK
t_CDOFF
t_IFG
RXD
101010100
Note: RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 19. Mode 2 RCLK/EOP Timing
21