MB85R1001_09 Datasheet, PDF (3/12 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 1 M Bit (128 K × 8)

MB85R1001
■ BLOCK DIAGRAM
A0
·
to ·
·
Row Dec. Ferro Capacitor Cell
A16
intCE2
Column Dec.
CE2
intCEB
WE
OE
intCE2
intOE
intWE
intCE2
S/A
I/O1 to I/O8
CE1
intCEB
I/O8
· _to
·
I/O1
■ FUNCTION TRUTH TABLE
Operation Mode
CE1 CE2 WE OE
H
X
X
X
Standby Pre-charge
X
L
X
X
X
X
H
H
Read
H
H
L
L
Read
(Pseudo-SRAM, OE control*¹)
L
H
H
Write
H
L
H
L
Write
(Pseudo-SRAM, WE control*²)
L
H
H
I/O1 to I/O8
High-Z
Supply Current
Standby
(ISB)
Dout
Din
Operation
(ICC)
L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
: Latch address and latch data at falling edge, : Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
DS05-13103-7E
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