MB85R1001_09 Datasheet, PDF (10/12 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 1 M Bit (128 K × 8)

MB85R1001
■ POWER ON/OFF SEQUENCE
tpd
VCC
CE2
3.0 V
VIH (Min)
tr
tpu
VCC
CE2
3.0 V
VIH (Min)
1.0 V
VIL (Max)
GND
CE2 ≤ 0.2 V
CE1 > VCC × 0.8*
CE1 : Don't Care
CE1 > VCC × 0.8*
1.0 V
VIL (Max)
GND
CE1
CE1
* : CE1 (Max) < VCC + 0.5 V
Notes: • Use either of CE1 or CE2, or both for disenable control of the device.
• Because turning the power-on from an intermediate level cause malfunction, when the
power is turned on, VCC is required to be started from 0 V.
• If the device does not operate within the specified conditions of read cycle, write cycle,
power on/off sequence, memory data can not be guaranteed.
Parameter
CE1 level hold time for Power OFF
CE1 level hold time for Power ON
Power supply rising time
Sym-
bol
tpd
tpu
tr
(within recommended operating conditions)
Value
Min
Typ
Unit
Max
85
⎯
⎯
ns
85
⎯
⎯
ns
0.05
⎯
200
ms
■ NOTES ON USE
After the IR reflow completed, it is not guaranteed to save the data written prior to the IR reflow.
■ ORDERING INFOMATION
Part number
MB85R1001PFTN-GE1
Package
48-pin plastic TSOP(1)
(FPT-48P-M25)
10
DS05-13103-7E