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MC9RS08KA2_07 Datasheet, PDF (99/136 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
Chapter 12 Development Support
HIGH IMPEDANCE
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
HIGH IMPEDANCE
R-C RISE
HIGH IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES BKGD PIN
EARLIEST START
OF NEXT BIT
Figure 12-4. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 12-5 shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous to
the target, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the
bit time as perceived by the target. The host initiates the bit time but the target ï¬nishes it. Because the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then brieï¬y drives
it high to speed up the rising edge. The host samples the bit level approximately 10 cycles after starting the
bit time.
MC9RS08KA2 Series Data Sheet, Rev. 3
Freescale Semiconductor
99
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