MC9RS08KA2_07 Datasheet, PDF (79/136 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Internal Clock Source (RS08ICSV1)
9.5.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when CLKS is
written to 0.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency.
9.5.1.2 FLL Bypassed Internal (FBI)
The FLL bypassed internal (FBI) mode is entered when CLKS is written to 1 and LP bit is a 0.
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency.
9.5.1.3 FLL Bypassed Internal Low Power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when CLKS is written to 1 and LP = 1.
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled.
9.5.1.4 Stop
ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clocks are stopped except
ICSIRCLK which will remaining running if IREFSTEN is written to a 1.
When the MCU is interrupted from stop, the ICS will go back to the operating mode that was running when
the MCU entered stop. If the internal reference was not running in stop (IREFSTEN = 0), the ICS will take
some time, t_{ir_wu}, for the internal reference to wakeup. If the internal reference was already running in stop
(IREFSTEN = 1), entering into FEI will take some time, t_{fll_wu}, for the FLL to return its previous acquired
frequency.
9.5.2 Mode Switching
When changing from FBILP to either FEI or FBI, or anytime the trim value is written, the user should wait
the FLL acquisition time, t_acquire, before FLL will be guaranteed to be at desired frequency.
9.5.3 Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
9.5.4 Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not
being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for
MC9RS08KA2 Series Data Sheet, Rev. 3
Freescale Semiconductor
79