MC9RS08KA2_07 Datasheet, PDF (75/136 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Internal Clock Source (RS08ICSV1)
9.2.2.4 Stop (STOP)
In stop mode, the FLL is disabled and the internal reference clocks can be selected to be enabled or
disabled. The ICS does not provide an MCU clock source.
9.2.3 Block Diagram
Figure 9-2 shows the ICS block diagram.
IREFSTEN
Internal
Reference
Clock
(32 kHz)
CLKS
BDIV
/ 2ⁿ
LP
n=0-3
ICSIRCLK
ICSOUT¹
9
TRIM
DCO
9
Filter
FLL
DCOOUT
ICSIRCLK
/2
ICSFFCLK
1 _{ICSOUT is two times the bus frequency}
Figure 9-2. Internal Clock Source (ICS) Block Diagram
9.3 External Signal Description
No ICS signal connects off chip.
MC9RS08KA2 Series Data Sheet, Rev. 3
Freescale Semiconductor
75