MC9RS08KA2_07 Datasheet, PDF (80/136 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Internal Clock Source (RS08ICSV1)
maximum accuracy before switching to an FLL engaged mode. The FLL is disabled in bypass mode when
LP = 1.
9.5.5 Internal Reference Clock
The ICSIRCLK frequency can be re-targeted by trimming the period of the internal reference clock. This
can be done by writing a new value to the TRIM bits in the ICSTRM register. Writing a larger value will
slow down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM register will speed up
the ICSIRCLK frequency. The TRIM bits will affect the ICSOUT frequency if the ICS is in FLL engaged
internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. The
TRIM and FTRIM values will not be affected by a reset. For the ICS to run in stop, the LVDE and LVDSE
bits in the SPMSC1 must both be set before entering stop.
Until ICSIRCLK is trimmed, ICSOUT frequencies may exceed the maximum chip-level frequency and
violate the chip-level clock timing specifications (see the Device Overview chapter). The BDIV is reset to
a divide by 2 to prevent the bus frequency from exceeding the maximum. The user should trim the device
to an allowable frequency before changing BDIV to a divide by 1 operation.
9.5.6 Fixed Frequency Clock
The ICS provides the ICSFFCLK output which can be used as an additional clock source to a peripheral
such as a timer, when the ICS is in FEI. ICSFFCLK is not a valid clock source for a peripheral when in
either FBI or FBILP modes. ICSFFCLK is ICSRCLK divided by two.
MC9RS08KA2 Series Data Sheet, Rev. 3
80
Freescale Semiconductor