56F8033 Datasheet, PDF (97/157 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.3.17.9 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.17.10 Configure GPIOB0 (GPS_B0)—Bits 0
This field selects the alternate function for GPIOB0.
• 0 = SCLK0 - QSPI0 Serial Clock (default)
• 1 = SCL - I²C Serial Clock
6.3.18 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 _{GPS_}
B7
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-21 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
6.3.18.1 Reserved—Bits 15–1
This bit field is reserved. Each bit must be set to 0.
6.3.18.2 Configure GPIOB7 (GPS_B7)—Bit 0
This field selects the alternate function for GPIOB7.
• 0 = TXD0 - QSCI0 Transmit Data (default)
• 1 = SCL - I²C Serial Clock
6.3.19 Internal Peripheral Source Select Register 0 for Pulse Width
Modulator (SIM_IPS0)
The internal integration of peripherals provides input signal source selection for peripherals where an input
signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral
type and provide a selection list for every peripheral input signal that has more than one alternative source
to indicate which source is selected.
If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the
settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select
an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral
input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control
of the I/O.
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
97