56F8033 Datasheet, PDF (112/157 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Add.
Offset
Register Acronym
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
$0 GPIOA_PUPEN W
PU[15:0]
RS 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R
$1
GPIOA_DATA W
D[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$2
GPIOA_DDIR W
DD[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$3 GPIOA_PEREN W
PE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$4 GPIOA_IASSRT W
IA[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$5
GPIOA_IEN
W
IEN[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$6
GPIOA_IEPOL W
IEPOL[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
IPR[15:0]
$7
GPIOA_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$8
GPIOA_IEDGE W
IES[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$9 GPIOA_PPOUTM W
OEN[15:0]
RS 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R
RAW DATA[15:0]
$A GPIOA_RDATA W
RS 0 X X X X X X X X X X X X X X X
R
$B
GPIOA_DRIVE W
DRIVE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 Read as 0
W
Reserved
RS
Reset
Figure 8-1 GPIOA Register Map Summary
56F8033/56F8023 Data Sheet, Rev. 6
112
Freescale Semiconductor