MC9S12XEP100_07 Datasheet, PDF (888/1430 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
Table 24-8. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6–0
FDIV[6:0]
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 24-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 24.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
MC9S12XE-Family Reference Manual , Rev. 1.14
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