MC9S12XEP100_07 Datasheet, PDF (708/1430 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.4.1 Timer
As shown in Figure 17-1 and Figure 17-27, the 24-bit timers are built in a two-stage architecture with eight
16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with
two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer
is connected to micro time base 0 or 1 via the PMUX[7:0] bit setting in the PIT Multiplex (PITMUX)
register.
A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer
(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register
is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro
time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter
will load its start value as specified in the PITMTLD0 or PITMTLD1 register and will start down-counting.
Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the
connected 16-bit modulus down-counters count one cycle.
MC9S12XE-Family Reference Manual , Rev. 1.14
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Freescale Semiconductor