MC9S12XEP100_07 Datasheet, PDF (1308/1430 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Appendix A Electrical Characteristics
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V_SS35 or V_DD35).
Table A-1. Absolute Maximum Ratings¹
Num
Rating
Symbol
Min
Max
Unit
1 I/O, regulator and analog supply voltage
2 Digital logic supply voltage²
3 PLL supply voltage²
4 NVM supply voltage²
5 Voltage difference V_DDX to V_DDA
6 Voltage difference V_SSX to V_SSA
7 Digital I/O input voltage
8 Analog reference
9 EXTAL, XTAL
10 TEST input
11 Instantaneous maximum current
Single pin limit for all digital I/O pins³
V_DD35
V_DD
V_DDPLL
V_DDF
∆_VDDX
∆_VSSX
V_IN
V_RH, V_RL
V_ILV
V_TEST
I_D
–0.3
–0.3
–0.3
–0.3
–6.0
–0.3
–0.3
–0.3
–0.3
–0.3
–25
6.0
V
2.16
V
2.16
V
3.6
V
0.3
V
0.3
V
6.0
V
6.0
V
2.16
V
10.0
V
+25
mA
12 Instantaneous maximum current
Single pin limit for EXTAL, XTAL⁴
I_DL
–25
+25
mA
13 Instantaneous maximum current
Single pin limit for TEST ⁵
I_DT
–0.25
0
mA
14 Maximum current
Single pin limit for power supply pins
I_DV
–100
+100
mA
15 Storage temperature range
Tstg
–65
155
°C
1 ^{Beyond absolute maximum ratings device might be damaged.}
2 ^{The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute}
maximum ratings apply when the device is powered from an external source.
3 ^{All digital I/O pins are internally clamped to V}SSX ^{and V}DDX^{, or V}SSA ^{and V}DDA^.
4 ^{Those pins are internally clamped to V}SSPLL ^{and V}DDPLL^.
5 ^{This pin is clamped low to V}SSPLL^{, but not clamped high. This pin must be tied low in applications.}
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
1308
MC9S12XE-Family Reference Manual , Rev. 1.14
Freescale Semiconductor