MC9S12XEP100_07 Datasheet, PDF (863/1430 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
23.3.2 Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
23.3.2.1 HT Control Register (VREGHTCL)
0x02F0
7
R
0
W
6
5
4
0
VSEL
VAE
Reset
0
0
0
1
= Unimplemented or Reserved
3
HTEN
0
2
HTDS
0
1
HTIE
0
0
HTIF
0
23.3.2.2 Control Register (VREGCTRL)
Table 23-4. VREGHTCL Field Descriptions
Field
Description
7, 6
Reserved
5
VSEL
4
VAE
3
HTEN
2
HTDS
1
HTIE
0
HTIF
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
Voltage Access Select Bit — If set, the bandgap reference voltage V_BG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). . The internal access must be enabled by bit
VAE. See device level specification for connectivity.
0 An internal voltage can be accessed internally if VAE is set.
1 Bandgap reference voltage V_BG can be accessed internally if VAE is set.
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
High Temperature Detect Status Bit —
0 Temperature T_DIE is below level T_HTID or RPM or Shutdown Mode.
1 Temperature T_DIE is above level T_HTIA and FPM.
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
High Temperature Interrupt Flag —
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
MC9S12XE-Family Reference Manual Rev. 1.14
Freescale Semiconductor
863