MC68HC908QY2CDW Datasheet, PDF (87/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

LVI Status Register
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was detected below the V_TRIPF level while
LVI resets have been disabled.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_TRIPF trip voltage and is cleared
when V_DD voltage rises above V_TRIPR. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.
Table 10-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
87