MC68HC908QY2CDW Datasheet, PDF (106/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum t_RL time. Figure 13-3 shows the relative timing. The RST pin function is only available
if the RSTEN bit is set in the CONFIG2 register.
BUSCLKX2
RST
ADDRESS BUS PC
VECT H VECT L
Figure 13-3. External Reset Timing
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 13-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 13-5).
IRST
RST
BUSCLKX4
ADDRESS
BUS
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 13-4. Internal Reset Timing
VECTOR HIGH
MC68HC908QY/QT Family Data Sheet, Rev. 6
106
Freescale Semiconductor