MC68HC908QY2CDW Datasheet, PDF (30/184 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory
Addr.
$0039
↓
$003B
Register Name
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
ADC Status and Control ^{Read: COCO}
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
$003C
Register (ADSCR) Write: R
See page 45. _{Reset: 0}
0
0
1
1
1
1
1
$003D
Unimplemented
$003E
ADC Data Register ^Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(ADR) Write:
See page 47. _Reset:
Indeterminate after reset
ADC Input Clock Register ^Read: _ADIV2
ADIV1
ADIV0
0
0
0
0
0
$003F
(ADICLK) Write:
See page 47. _{Reset: 0}
0
0
0
0
0
0
0
Break Status Register ^Read:
R
R
R
R
R
SBSW
R
R
$FE00
(BSR) Write:
See note 1
See page 137. _Reset:
0
1. Writing a 0 clears SBSW.
SIM Reset Status Register ^{Read: POR}
PIN
$FE01
(SRSR) Write:
See page 117. _{POR: 1}
0
Break Auxiliary ^{Read: 0}
0
$FE02
Register (BRKAR) Write:
See page 137. _{Reset: 0}
0
$FE03
Break Flag Control ^Read: _BCFE
R
Register (BFCR) Write:
See page 138. _{Reset: 0}
Interrupt Status Register 1 ^{Read: 0}
IF5
$FE04
(INT1) Write: R
R
See page 77. _{Reset: 0}
0
Interrupt Status Register 2 ^{Read: IF14}
0
$FE05
(INT2) Write: R
R
See page 77. _{Reset: 0}
0
Interrupt Status Register 3 ^{Read: 0}
0
$FE06
(INT3) Write: R
R
See page 77. _{Reset: 0}
0
$FE07
Reserved
R
R
COP
ILOP
ILAD MODRST LVI
0
0
0
0
0
0
0
0
0
0
0
0
BDCOP
0
0
0
0
0
0
R
R
R
R
R
R
IF4
IF3
0
IF1
0
0
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
IF15
R
R
R
R
R
R
0
0
0
0
0
0
R
R
R
R
R
R
= Unimplemented
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 6
30
Freescale Semiconductor