MC9S08JM60 Datasheet, PDF (85/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
7
R
W
Reset
0
6
5
4
3
2
PTAPE5
PTAPE4
PTAPE3
PTAPE2
0
0
0
0
0
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
1
PTAPE1
0
0
PTAPE0
0
Table 6-3. PTADD Register Field Descriptions
Field
Description
[5:0]
PTAPE[5:0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
7
R
W
6
5
4
3
2
1
0
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
Reset
0
0
1
1
1
1
1
1
Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field
Description
5:0
PTASE[5:0]
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
7
R
W
Reset
0
6
5
4
3
2
1
PTADS5
PTADS4
PTADS3
PTADS2
PTADS1
0
0
0
0
0
0
Figure 6-6. Output Drive Strength Selection for Port A (PTASE)
0
PTADS0
0
Table 6-5. PTASE Register Field Descriptions
Field
Description
5:0
PTADS[5:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
MC9S08JM60 Series Data Sheet, Rev. 2
Freescale Semiconductor
85