MC9S08JM60 Datasheet, PDF (136/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
ADCH
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
Channel
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
Table 10-1. ADC Channel Assignment
Input
PTB0/MISO2/ADP0
PTB1/MOSI2/ADP1
PTB2/SPSCK2/ADP2
PTB3/SS2/ADP3
PTB4/KBIP4/ADP4
PTB5/KBIP5/ADP5
PTB6/ADP6
PTB7/ADP7
PTD0/ADP8/ACMP+
PTD1/ADP9/ACMP-
PTD3/KBIP3/ADP10
Pin Control
ADPC0
ADPC1
ADPC2
ADPC3
ADPC4
ADPC5
ADPC6
ADPC7
ADPC8
ADPC9
ADPC10
ADCH
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
Channel
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
01011
01100
01101
01110
01111
AD11
AD12
AD13
AD14
AD15
PTD4/ADP11
V_REFL
V_REFL
V_REFL
V_REFL
ADPC11
ADPC12
ADPC13
ADPC14
ADPC15
11011
11100
11101
11110
11111
1 _{For more information, see Section 10.1.1.5, “Temperature Sensor.”}
AD27
V_REFH
V_REFL
module
disabled
Input
V_REFL
V_REFL
V_REFL
V_REFL
V_REFL
Reserved
Reserved
Reserved
Reserved
Reserved
Temperature
Sensor¹
Internal Bandgap
Reserved
V_REFH
V_REFL
None
Pin Control
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NOTE
Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see
Section 5.7.7, “System Power Management Status and Control 1 Register
(SPMSC1).” For value of bandgap voltage reference see Appendix A.8,
“Analog Comparator (ACMP) Electricals.”
10.1.1.2 Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
the local asynchronous clock (ADACK) within the module, or the alternate clock (ALTCLK). The
ALTCLK on this device is the MCGERCLK.
The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a
frequency within its specified range (f_ADCK) after being divided down from the ALTCLK input as
determined by the ADIV bits.
ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This
allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in stop3.
10.1.1.3 Hardware Trigger
The RTC on this device can be enabled as a hardware trigger for the ADC module by setting the
MC9S08JM60 Series Data Sheet, Rev. 2
136
Freescale Semiconductor