MC9S08JM60 Datasheet, PDF (84/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin
control registers. This section refers to registers and control bits only by their names. A Freescale-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.5.1 Port A I/O Registers (PTAD and PTADD)
Port A parallel I/O function is controlled by the registers listed below.
7
R
W
Reset
0
6
5
4
3
2
1
0
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
0
0
0
0
0
0
Figure 6-2. Port A Data Register (PTAD)
Table 6-1. PTAD Register Field Descriptions
Field
Description
5:0
PTAD[5:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
R
W
Reset
0
6
5
4
3
2
1
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
0
0
0
0
0
0
Figure 6-3. Data Direction for Port A Register (PTADD)
0
PTADD0
0
Table 6-2. PTADD Register Field Descriptions
Field
Description
5:0
PTADD[5:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
MC9S08JM60 Series Data Sheet, Rev. 2
84
Freescale Semiconductor