MC9S12XEP100 Datasheet, PDF(840/1036 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC9S12XEP100 Datasheet, PDF (840/1036 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Chapter 22 Voltage Regulator (S12VREGL3V3V1)

22.4.2 Regulator Core (REG)

Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).

REG1 and REG3 differ only in the amount of current that can be delivered.

The regulators are linear regulator with a bandgap reference when operated in Full Performance Mode.

They act as a voltage clamp in Reduced Power Mode. All load currents ï¬ow from input VDDR to VSS or

VSSPLL. The reference circuits are supplied by VDDA and VSSA.

22.4.2.1 Full Performance Mode

In Full Performance Mode, the output voltage is compared with a reference voltage by an operational

ampliï¬er. The ampliï¬ed input voltage difference drives the gate of an output transistor.

22.4.2.2 Reduced Power Mode

In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to

reduce power consumption. Mode switching from reduced power to full performance requires a transition

time of tvup, if the voltage regulator is enabled.

22.4.3 Low-Voltage Detect (LVD)

Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input

voltage (VDDAâVSSA) and continuously updates the status ï¬ag LVDS. Interrupt ï¬ag LVIF is set whenever

status ï¬ag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode

or Shutdown Mode.

22.4.4 Power-On Reset (POR)

This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD,

the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on

sequence.

22.4.5 Low-Voltage Reset (LVR)

Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below itâs

corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their

corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full

Performance Mode.

22.4.6 Regulator Control (CTRL)

This part contains the register block of VREG_3V3 and further digital functionality needed to control the

operating modes. CTRL also represents the interface to the digital core logic.

MC9S12XE-Family Reference Manual , Rev. 1.07

840

Freescale Semiconductor

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