MC9S12XEP100 Datasheet, PDF (576/1036 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.29 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0031
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
PBOVF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-51. Pulse Accumulator B Flag Register (PBFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 14-36. PBFLG Field Descriptions
Field
1
PBOVF
Description
Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from
0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000.
When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active
edge follows on PT1.
MC9S12XE-Family Reference Manual , Rev. 1.07
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Freescale Semiconductor