MC9S12XEP100 Datasheet, PDF (83/1036 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2
Port Integration Module (S12XEPIMV1)
Revision History
Rev. No.
Date
(Item No.) (Submitted By)
Sections
Affected
Substantial Change(s)
V01.13
V01.14
18 Jul 2006
01 Aug 2006
2.3.5/2-103
2.3.17/2-112
2.3.1/2-93
Corrected DDRA address.
Removed ‘PRR’ from IRQCR register.
Revised PAD0 and PAD1 register bit names.
V01.15
16 Apr 2007
2.3.69/2-149
2.3.70/2-149
2.3.77/2-153
2.3.78/2-154
2.4.3.12/2-179
2.4.3.13/2-179
Corrected ATD pin mappings
2.1 Introduction
2.1.1 Overview
The S12XE Family Port Integration Module establishes the interface between the peripheral modules
including the non-multiplexed External Bus Interface module (S12X_EBI) and the I/O pins for all ports.
It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
This document covers:
• Port A and B used as address output of the S12X_EBI
• Port C and D used as data I/O of the S12X_EBI
• Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs
• Port K associated with address output and control signals of the S12X_EBI
• Port T associated with 1 ECT module
• Port S associated with 2 SCI and 1 SPI modules
• Port M associated with 4 MSCAN and 1 SCI module
• Port P connected to the PWM and 2 SPI modules - inputs can be used as an external interrupt source
• Port H associated with 4 SCI modules - inputs can be used as an external interrupt source
• Port J associated with 1 MSCAN, 1 SCI, 2 IIC modules and chip select outputs - inputs can be used
as an external interrupt source
MC9S12XE-Family Reference Manual , Rev. 1.07
Freescale Semiconductor
83