MC9S12XEP100 Datasheet, PDF (257/1036 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
5.5.1 Normal Expanded Mode
This mode allows interfacing to external memories or peripherals which are available in the commercial
market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each
external access.
5.5.1.1 Example 1a: External Wait Feature Disabled
The first example of bus timing of an external read and write access with the external wait feature disabled
is shown in
• Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’
The associated supply voltage dependent timing are numbers given in
• Table ‘Example 1a: Normal Expanded Mode Timing V_DD5 = 5.0 V (EWAIT disabled)’
• Table ‘Example 1a: Normal Expanded Mode Timing V_DD5 = 3.0 V (EWAIT disabled)’
Systems designed this way rely on the internal programmable access stretching. These systems have
predictable external memory access times. The additional stretch time can be programmed up to 8 cycles
to provide longer access times.
5.5.1.2 Example 1b: External Wait Feature Enabled
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles
over the programmed number in EXSTR[2:0]. The feature must be enabled by configuring at least one
CSx line for EWAIT.
If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If
EWAIT is asserted within the predefined time window during the access it will be strobed active and
another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is
finished. EWAIT can be held asserted as long as desired to stretch the access.
An access with 1 cycle stretch by EWAIT assertion is shown in
• Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’
• Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’
The associated timing numbers for both operations are given in
• Table ‘Example 1b: Normal Expanded Mode Timing V_DD5 = 5.0 V (EWAIT enabled)’
• Table ‘Example 1b: Normal Expanded Mode Timing V_DD5 = 3.0 V (EWAIT enabled)’
It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize
the EWAIT input signal.
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
257