MC9S12XEP100 Datasheet, PDF (169/1036 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-95. PTF Register Field Descriptions (continued)
Field
1
PTF
0
PTF
Description
Port F general purpose input/output data—Data Register
Port F pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port F general purpose input/output data—Data Register
Port F pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.102 Port F Input Register (PTIF)
Address 0x0379
7
R PTIF7
6
PTIF6
5
PTIF5
4
PTIF4
3
PTIF3
2
PTIF2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-100. Port F Input Register (PTIF)
1 _{Read: Anytime.}
Write:Never, writes to this register have no effect.
Access: User read¹
1
PTIF1
0
PTIF0
u
u
Field
7-0
PTIF
Table 2-96. PTIF Register Field Descriptions
Description
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.103 Port F Data Direction Register (DDRF)
Address 0x037A
R
W
Reset
7
DDRF7
0
1 _{Read: Anytime.}
Write: Anytime.
6
DDRF6
5
DDRF5
4
DDRF4
3
DDRF3
2
DDRF2
0
0
0
0
0
Figure 2-101. Port F Data Direction Register (DDRF)
Access: User read/write¹
1
0
DDRF1
DDRF0
0
0
MC9S12XE-Family Reference Manual Rev. 1.07
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