MC68HC05E5 Datasheet, PDF (81/140 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
M-Bus Registers
MTX — Transmit/Receiver Mode Select Bit
This bit selects the direction of master and slave transfers. When
addressed as a slave, this bit should be set by software according to
the SRW bit in the status register. In master mode, this bit should be
set according to the type of transfer required. Hence, for address
cycles this bit will always be high.
1 = Transmit
0 = Receive
TXAK — Transmit Acknowledge Enable Bit
If TXAK is cleared, an acknowledge signal will be sent out to the bus
at the ninth clock bit after receiving one byte of data. When TXAK is
set, there will be no acknowledge signal response (for example,
acknowledge bit = 1).
MMUX — M-Bus Multiplexer
This bit is used to enable PB7 and PB6 to be under the control of the
M-bus circuit. When set, both PB7 and PB6 become open-collector
outputs or inputs when enabled by the M-bus control. When cleared
PB7 and PB6 are under control of the port DDR logic. This bit can be
set or cleared independent of the MEN bit. Caution should be used if
PB7 and PB6 are used as general-purpose I/O.
1 = M-bus control
0 = POR condition, port B DDR control
MC68HC05E5 — Rev. 1.0
General Release Specification
Motorola Bus (M Bus) Interface
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