MC68HC05E5 Datasheet, PDF (43/140 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
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Computer Operating Properly Reset (COPR)
5.6 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to timeout, an internal reset is generated
to reset the MCU. Regardless of an internal or external reset, the MCU
comes out of a COP reset according to the standard rules of mode
selection.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
5.6.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPF bit. This
action will reset the counter and begin the timeout period again. The
COPF bit is bit 0 of address $1FF0. A read of address $1FF0 will return
user data programmed at that location.
5.6.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPF bit to prevent a COP reset.
5.6.3 COP During Stop Mode
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
MC68HC05E5 — Rev. 1.0
General Release Specification
Resets
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