MC68HC05E5 Datasheet, PDF (37/140 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Interrupts
Custom Periodic Interrupt (CPI)
4.7 Custom Periodic Interrupt (CPI)
The CPI flag and enable bits are located in the CPI control and status
register (CPICSR). A CPI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
location $1FF6 and $1FF7.
The custom periodic interrupt is mask programmable to a 0.25 second,
0.5 second, or 1 second interrupt. The interrupt is generated from the
32-kHz OSC1 input by a 15-bit counter. This interrupt is under the
control of the custom periodic interrupt control and status register
located at $12.
Address $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
CPIF
0
CPIE
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 4-3. Custom Periodic Interrupt Control
and Status Register (CPICSR)
CPIF — Custom Periodic Interrupt Flag
CPIF is a clearable, read-only status bit and is set when the 15-bit
counter changes from $7FFF to $0000. A CPU interrupt request will
be generated if CPIE is set. Clearing the CPIF is done by writing a
zero to it. Writing a one to CPIF has no effect on the bit’s value. Reset
clears CPIF.
CPIE — Custom Periodic Interrupt Enable
When this bit is cleared, the CPI interrupts are disabled. When this bit
is set, the CPU interrupt request is generated when the CPIF bit is set.
Reset clears this bit.
MC68HC05E5 — Rev. 1.0
General Release Specification
Interrupts
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