MC68HC05E5 Datasheet, PDF (73/140 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
M-Bus Protocol
11.5.2 Slave Address Transmission
Immediately after the start signal, the first byte of data transfer is the
slave address transmitted by the master. This data is a 7-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a matched address will respond by sending back an
acknowledge bit. This acknowledge bit is accomplished by pulling SDA
low on the ninth clock cycle. (See Figure 11-1.)
11.5.3 Data Transfer
Once a successful slave addressing is achieved, the data transfer can
proceed byte by byte in the direction specified by the R/W bit sent by the
calling master.
Each data byte is eight bits long. Data can be changed only when SCL
is low and must be held stable while SCL is high as shown in Figure
11-1. The MSB is transmitted first and each byte has to be followed by
an acknowledge bit. The acknowledge bit is signalled by the receiving
device by pulling the SDA low on the ninth clock cycle. Therefore, one
complete data byte transfer needs nine clock cycles.
If the slave receiver does not acknowledge the master, the SDA line
should be left high by the slave. The master can then generate a stop
signal to abort the data transfer or a start signal (repeated start) to
commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after
a byte has been transmitted, it means an “end of data” to the slave. The
slave should now release the SDA line for the master to generate a stop
or start signal.
MC68HC05E5 — Rev. 1.0
General Release Specification
Motorola Bus (M Bus) Interface
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