MC68HC05E5 Datasheet, PDF (103/140 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
SSI During Wait Mode
12.6 SSI During Wait Mode
The CPU clock halts during wait mode, but the SSI remains active. If
interrupts are enabled, an SSI interrupt will cause the processor to exit
wait mode.
12.7 SSI Pin Configuration
When the SSI is enabled via the SE bit of the SCR ($0A), the port B data
direction register bits 3–5 relinquish control to the SSI as directed by the
combination of the SE, MSTR, and SDIR bits. The states of the port B
DDR bits are not altered by the SSI.
MC68HC05E5 — Rev. 1.0
General Release Specification
Synchronous Serial Interface (SSI)
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