MC9S08QA4_09 Datasheet, PDF (8/32 Pages) Freescale Semiconductor, Inc – Technical Data

Electrical Characteristics
Table 6. DC Characteristics (Temperature Range = –40 to 85°C Ambient) (continued)
Parameter
Symbol
Min
Typical
Max
Unit
Power on reset (POR) re-arm voltage
(V_DD rising)
Bandgap voltage reference
Input high voltage (V_DD > 2.3 V) (all digital inputs)
Input high voltage (1.8 V ≤ V_DD ≤ 2.3 V) (all digital inputs)
Input low voltage (V_DD > 2.3 V) (all digital inputs)
Input low voltage (1.8 V ≤ V_DD ≤ 2.3 V) (all digital inputs)
Input hysteresis (all digital inputs)
Input leakage current (per pin)
V_In = V_DD or V_SS, all input-only pins
High impedance (off-state) leakage current (per pin)
V_In = V_DD or V_SS, all input/output
Internal pullup resistors^3,4
Internal pulldown resistor (KBI)
Output high voltage — low drive (PTxDSn = 0)
I_OH = –2 mA (V_DD ≥ 1.8 V)
Output high voltage — high drive (PTxDSn = 1)
I_OH = –10 mA (V_DD ≥ 2.7 V)
I_OH = –6 mA (V_DD ≥ 2.3 V)
I_OH = –3 mA (V_DD ≥ 1.8 V)
Maximum total I_OH for all port pins
Output low voltage — low drive (PTxDSn = 0)
I_OL = 2.0 mA (V_DD ≥ 1.8 V)
Output low voltage — high drive (PTxDSn = 1)
I_OL = 10.0 mA (V_DD ≥ 2.7 V)
I_OL = 6 mA (V_DD ≥ 2.3 V)
I_OL = 3 mA (V_DD ≥ 1.8 V)
Maximum total I_OL for all port pins
DC injection current ^{2, 5, 6, 7}
V_In < V_SS, V_In > V_DD
Single pin limit
Total MCU limit, includes sum of all stressed pins
V_por
V_BG
V_IH
V_IL
V_hys
|I_In|
|I_OZ|
R_PU
R_PD
V_OH
|I_OHT|
V_OL
I_OLT
I_IC
2.16
—
1.18
0.70 × V_DD
0.85 × V_DD
—
—
0.06 × V_DD
—
—
17.5
17.5
V_DD – 0.5
V_DD – 0.5
—
—
—
—
—
—
–0.2
–5
2.19
1.4
1.20
—
—
—
—
—
0.025
0.025
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.27
—
V
1.21
V
—
V
—
0.35 × V_DD
V
0.30 × V_DD
—
V
1.0
μA
1.0
μA
52.5
kΩ
52.5
kΩ
—
V
—
—
—
60
mA
0.5
V
0.5
0.5
0.5
60
mA
0.2
mA
5
mA
Input capacitance (all non-supply pins)
C_In
—
—
7
pF
1 _{RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR.}
2 _{This parameter is characterized and not tested on each device.}
3 _{Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.}
4 _{PTA5/IRQ/TCLK/RESET pullup resistor may not pull up to the specified minimum VIH. However, all ports are functionally tested}
to guarantee that a logic 1 will be read on any port input when the pullup is enabled and no DC load is present on the pin.
5 _{All functional non-supply pins are internally clamped to VSS and VDD.}
MC9S08QA4 Series MCU Data Sheet, Rev. 3
8
Freescale Semiconductor