MC9S08QA4_09 Datasheet, PDF (13/32 Pages) Freescale Semiconductor, Inc – Technical Data

Electrical Characteristics
3.8.1 Control Timing
Table 9. Control Timing
Parameter
Symbol
Min
Typical¹
Max
Unit
Bus frequency (t_cyc = 1/f_Bus)
Real-time interrupt internal oscillator period (see Table 9)
External reset pulse width²
IRQ pulse width
Asynchronous path²
Synchronous path³
KBIPx pulse width
Asynchronous path²
Synchronous path³
Port rise and fall time (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
f_Bus
t_RTI
t_extrst
t_ILIH
t_ILIH, t_IHIL
t_Rise, t_Fall
0
700
100
100
1.5 t_cyc
100
1.5 t_cyc
—
—
—
1000
—
—
—
3
30
10
1300
—
—
MHz
μs
ns
ns
—
ns
—
ns
—
BKGD/MS setup time after issuing background debug force
t_MSSU
500
—
reset to enter user or BDM modes
—
ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes⁵
t_MSH
100
—
—
μs
1 _{Data in Typical column was characterized at 3.0 V, 25°C.}
2 _{This is the shortest pulse that is guaranteed to be recognized.}
3 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
5 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
1600
1400
1200
1000
Period (μs)
800
600
400
200
0
–40
–40
0
20
40
60
80
100
Temperature (°C)
Figure 9. Typical RTI Clock Period vs. Temperature
= +3 σ
= Mean
= –3 σ
MC9S08QA4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
13