MC9S08QA4_09 Datasheet, PDF (6/32 Pages) Freescale Semiconductor, Inc – Technical Data

Electrical Characteristics
Table 3. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Thermal resistance
Single-layer board
8-pin PDIP
8-pin NB SOIC
8-pin DFN
Thermal resistance
Four-layer board
8-pin PDIP
8-pin NB SOIC
8-pin DFN
Symbol
T_A
Value
T_L to T_H
–40 to 85
113
θ_JA
150
179
72
θ_JA
87
41
Unit
°C
°C/W
°C/W
The average chip-junction temperature (T_J) in °C can be obtained from:
T_J = T_A + (P_D × θ_JA)
Eqn. 1
where:
— T_A = Ambient temperature, °C
— θ_JA = Package thermal resistance, junction-to-ambient, °C/W
— P_D = P_int + P_I/O
— P_int = I_DD × V_DD, Watts — chip internal power
— P_I/O = Power dissipation on input and output pins — user-determined
For most applications, P_I/O << P_int and can be neglected. An approximate relationship between P_D and T_J (if P_I/O is neglected)
is:
P_D = K ÷ (T_J + 273°C)
Solving Equation 1 and Equation 2 for K gives:
Eqn. 2
K = P_D × (T_A + 273°C) + θ_JA × (P_D)²
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P_D (at equilibrium)
for a known T_A. Using this value of K, the values of P_D and T_J can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of T_A.
3.4 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
MC9S08QA4 Series MCU Data Sheet, Rev. 3
6
Freescale Semiconductor