MC9S08QA4_09 Datasheet, PDF (4/32 Pages) Freescale Semiconductor, Inc – Technical Data

Pin Assignments
Table 1. Pin Sharing Priority
PIN
Lowest
Priority
Highest
8-Pin Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
PTA5¹
IRQ
TCLK
RESET
2
PTA4
ACMPO BKGD
MS
3
V_DD
4
V_SS
5
PTA3
KBIP3
ADP3
6
PTA2
KBIP2
ADP2
7
PTA1
KBIP1
ADP1² ACMP–²
8
PTA0
KBIP0 TPMCH0 ADP0² ACMP+²
1 _{Pin does not contain a clamp diode to VDD and must not be driven}
above V_DD. The voltage measured on the internally pulled-up RESET
pin will not be pulled to V_DD. The internal gates connected to this pin
are pulled to V_DD.
2 _{If ACMP and ADC are both enabled, both will have access to the pin.}
PTA5/IRQ/TCLK/RESET ₁
PTA4/ACMPO/BKGD/MS 2
V_DD 3
V_SS 4
8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+
7 PTA1/KBIP1/ADP1/ACMP–
6 _{PTA2/KBIP2/ADP2}
5 _{PTA3/KBIP3/ADP3}
8-Pin PDIP/SOIC
PTA5/IRQ/TCLK/RESET ₁
PTA4/ACMPO/BKGD/MS ₂
V_{DD 3}
V_{SS 4}
8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+
7 PTA1/KBIP1/ADP1/ACMP–
6 _{PTA2/KBIP2/ADP2}
5 _{PTA3/KBIP3/ADP3}
8-Pin DFN
Figure 2. MC9S08QA4 Series in 8-Pin Packages
MC9S08QA4 Series MCU Data Sheet, Rev. 3
4
Freescale Semiconductor