33902 Datasheet, PDF (8/31 Pages) Freescale Semiconductor, Inc – High Speed CAN Interface with Embedded 5.0 V Supply

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ V_SUP ≤ 27 V, - 40°C ≤ T_A ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING (REF TO FIG 7)
TXD Dominant State Timeout
Bus dominant clamping detection
Propagation loop delay TXD to RXD, recessive to dominant
Propagation delay TXD to CAN, recessive to dominant
Propagation delay CAN to RXD, recessive to dominant
Propagation loop delay TXD to RXD, dominant to recessive
Propagation delay TXD to CAN, dominant to recessive
Propagation delay CAN to RXD, dominant to recessive
Loop time TXD to RXD, Slew rate 1 (Selected by P_SPI)
Rec to Dom
Dom to Rec
Loop time TXD to RXD, Slew rate 2 (Selected by P_SPI)
Rec to Dom
Dom to Rec
t_DOUT
300
600
900
µs
t_DOM
300
700
1000
µs
t_LRD
60
140
210
ns
t_TRD
-
70
110
ns
t_RRD
-
45
140
ns
t_LDR
50
120
200
ns
t_TDR
-
75
150
ns
t_RDR
-
50
140
ns
t_LOOPSL1
50
-
310
ns
t_LOOPSL2
50
-
310
ns
STATE MACHINE TIMING
External Wake-up Filter Time
3-Pulse pattern wake-up - Pulse width
V_DIFF = 1.15 V, Ta =-40°C
V_DIFF = 2.0 V, Ta =-40°C
V_DIFF = 1.15 V, 25°C ≤ Ta ≤ 125°C.
t_WAKE
-
10
t_PWIDTH
2.5
-
2.0
-
2.0
-
Time to report local wake-up event
t_{LOC WAKE-}
-
35
REP
Time to report CAN wake-up event
t_{CAN WAKE-}
-
25
REP
Device state transition time (P_SPI versus static mode change distinction)
t_DEV-TR
8.0
-
except from Standby and Go To Sleep modes
Transition time from Standby mode to any mode
t_LP-NP
-
35
Transition time from go to sleep to Sleep mode («Go To Sleep» command)
t_H
-
35
V_IO low to Sleep mode timing
t_{VIO- SLP}
-
10
V_DD low to CAN driver disable timing
t_VDD-CANOFF
-
10
V_DD low to regulator disable timing
t_VDDOFF
-
50
PSEUDO SPI (P_SPI)TIMING
P_SPI Operation frequency
FREQ
0.0625
-
SCLK Clock High Time
SCLK Clock Low Time
EN to Falling Edge of STBY
Falling Edge of STBY to EN
ERR rise Time
CL = 15 pF
t_WSCLKH
0.125
-
t_WSCLKL
0.125
-
t_SISU
40
-
t_SIH
40
-
t_RSO
-
25
ERR fall Time
CL = 15 pF
t_FSO
-
25
-
µs
µs
-
-
-
-
µs
-
µs
15
µs
-
µs
-
µs
-
ms
-
ms
-
ms
4.0
MHz
8.0
µs
8.0
µs
-
ns
-
ns
50
ns
50
ns
33902
8
Analog Integrated Circuit Device Data
Freescale Semiconductor