33902 Datasheet, PDF (17/31 Pages) Freescale Semiconductor, Inc – High Speed CAN Interface with Embedded 5.0 V Supply

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11 shows the meaning of the ERR pin versus the device state, the state transition and the events on TXD.
DEVICE MODE
NORMAL
STBY = 1
EN = 1
LISTEN ONLY
STBY = 1
EN = 0
ERR MEANING
WAKE-UP SOURCE
Local Wake-up => ERR low; CAN Wake-up => ERR high
4 dominant
pulses at TXD
BUS FAILURE,
VDDlow, Bus dom,
CANH or CANL short to GND
5.0 V or V_BAT => ERR low
STBY = 1
EN = 1
STBY = 1
EN = 1
STBY = 1
EN = 1
STBY = 1
EN = 0
STBY = 1
EN = 0
BATFAIL
V_SUP Low =>ERR high
STBY = 1
EN = 0
LOCAL FAILURE
VDD low, TXD-PD, RXD-PR, TXD short to RXD => ERR low
GO TO SLEEP
STANDBY
SLEEP
STBY = 0
EN = X
STBY = 0
EN = X
STBY = 0
EN = X
STBY = 0
EN = X
WAKE-UP EVENT
CAN Wake-up or Local Wake-up => ERR low
STBY = 0
EN = X
Figure 11. ERR versus device state
CAN INTERFACE DESCRIPTION:
CAN Interface Supply
The supply voltage for the CAN driver is the VDD pin. The
CAN interface also has a supply path from the battery line,
through the VSUP pin. This path is used in CAN Sleep mode
to allow wake-up detection.
During CAN communication (transmission and reception),
the CAN interface current is sourced from the VDD pin.
During CAN low power mode, the current is sourced from the
VSUP pin.
CAN Driver Operation in Normal Mode
The CAN driver will be enabled as soon as the device is in
Normal mode and the TXD pin is recessive.
When the CAN interface is in Normal mode, the driver has
two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
When TXD is high, the driver is set in the recessive state,
and CANH and CANL lines are biased to the voltage set at
VDD divided by 2, approx. 2.5 V.
When TXD is low, the bus is set into the dominant state,
and the CANL and CANH drivers are active. CANL is pulled
low and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL
voltage is compared versus an internal threshold (a few
hundred mV).
If “CANH minus CANL” is below the threshold, the bus is
recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is
dominant and RXD is set low.
The SPLIT pin is active and provide a 2.5 V biasing to the
SPLIT output.
Normal Mode and Slew Rate Selection
The CAN signal slew rate selection is done via the P_SPI.
By default, and if no P_SPI is used, the device is in the fastest
slew rate. Three slew rates are available. The slew rate
controls the recessive to dominant and dominant to recessive
transitions, which are also dependent on CANH and CANL
capacitance. This also affects the delay time from the TXD
pin to the bus, and from the bus to RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud rate
The minimum baud rate is determined by the shortest TXD
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
The shortest TXD dominant detection time of 300 μs leads
to a single bit time of: 300 μs / 12 = 25 μs.
So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33902
17